Thin film transistor array panel and manufacturing method thereof

ABSTRACT

A thin film transistor (TFT) array panel includes: an insulating substrate ( 110 ); first and second semiconductor members ( 151   a,b ) formed on the substrate and having opposite conductivity; a first gate member ( 121   a ) formed on a first layer ( 140 ), insulated from the first and the second semiconductor members and overlapping one of the first and the second semiconductor members; a second gate member ( 122   a ) formed on the first layer ( 140 ), separated from the first gate member, and insulated from the first and the second semiconductor members ( 151   a,b ), the second gate member ( 122   a ) not overlapping the first and the second semiconductor members; a first data member ( 162 ) formed on a second layer ( 160 ), connected to one of the first and the second semiconductor members ( 151   a,b ) and insulated from the first ( 121   a ) and the second ( 122   a ) gate members; and a first connection ( 123 ) formed on the second layer ( 160 ) and connecting the first gate member ( 121   a ) and the second gate member ( 122   a ).

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a thin film transistor array panel anda method thereof, and in particular, to a polysilicon thin filmtransistor array panel.

(b) Description of the Related Art

Thin film transistors (TFT) are used for driving pixels in a liquidcrystal display (LCD) and electro luminescence (EL) display. A panelincluding the TFTs also includes a plurality of gate lines transmittingscanning signals for turning on and off the TFTs and a plurality of datalines transmitting data signals for the display of the pixels.

The TFTs include polysilicon or amorphous silicon as active layers. Whenthe display panel includes polysilicon TFTs for switching the datasignals to be supplied to the pixels, driving circuits for generatingthe scanning signals and the data signals can be also formed on thedisplay panel along with the TFTs for the pixels such that cost andcomplexity for mounting driving chips are reduced.

The driving circuits include a plurality of driving TFTs, which have thesame layered structure as the TFTs for the pixels (referred to as “pixelTFTs” hereinafter). The driving circuits typical include both N typeTFTs and P type TFTs.

The TFTs include polysilicon members doped with N type or P typeimpurity. In order to both the N type and the P type polysiliconmembers, ion implantation is performed twice usually using the gatelines as an implantation mask. The gate lines exposed to the ionicimpurity are charged to yield electrostatic discharge (ESD) damages. TheESD damages are generated between adjacent gate members and they becomesevere when the sizes of the gate members are different since thevoltage difference become larger.

The large current due to the ESD makes damage on a gate insulating layerlocated between the gate lines and the silicon active layers and itmelts the silicon layers to be agglomerated or evaporated.

In order to ESD protection, protection diodes are formed in themanufacturing process. However, since the protection diodes areactivated after forming the data lines, there is no ESD protectionmechanism before the formation of the data lines.

Although a technique for minimizing the difference in the areas betweenadjacent gate members is suggested, there is difficulty in designing thegate members to fixed areas. In addition, this technique is somewhateffective in reducing defect ratio, but it is insufficient forpreventing the ESD damage due the difference in impurity doping amountbetween the gate members.

SUMMARY OF THE INVENTION

A motivation of the present invention is to provide a TFT array paneland a manufacturing method thereof for preventing ESD damage due toimpurity implantation.

A thin film transistor array panel is provided, which includes: aninsulating substrate; first and second semiconductor members formed onthe substrate and having opposite conductivity; a first gate memberinsulated from the first and the second semiconductor members andoverlapping one of the first and the second semiconductor members; asecond gate member formed on the same layer as the first gate member,separated from the first gate member, and insulated from the first andthe second semiconductor members, the second gate member not overlappingthe first and the second semiconductor members; a first data memberconnected to one of the first and the second semiconductor members andinsulated from the first and the second gate members; and a firstconnection formed on the same layer as the first data member andconnecting the first gate member and the second gate member.

The first and the second semiconductor members preferably includepolysilicon.

When the first gate member overlaps the first semiconductor member, theTFT array panel may further include a third gate member formed on thefirst layer, separated from the first and the second gate members,insulated from the first and the second semiconductor members, andoverlapping the second semiconductor member and may further include asecond connection formed on the second layer and connecting the secondgate member and the third gate member.

The TFT array panel may further include: a fourth gate member formed onthe first layer, separated from the first, the second, and the thirdgate members and insulated from the first and the second semiconductormembers, the fourth gate member not overlapping the first and the secondsemiconductor members; and a second connection formed on the secondlayer and connecting the third gate member and the fourth gate member.

The TFT array panel may further include: fifth and sixth gate membersformed on the first layer, separated from the first to the fourth gatemembers, insulated from the first and the second semiconductor members,and overlapping the first and the second semiconductor members,respectively; a seventh gate member formed on the first layer, separatedfrom the first to the sixth gate members and insulated from the firstand the second semiconductor members, the seventh gate member notoverlapping the first and the second semiconductor members; and thirdand fourth connections formed on the second layer and connecting thefifth and the sixth gate members to the seventh gate member.

The TFT array panel may further include a fifth connection formed on thesecond layer and connecting the first semiconductor member and thesecond semiconductor member.

The TFT array panel may further include: third and fourth semiconductormembers formed on the substrate and having opposite conductivity; eighthand ninth gate members formed on the first layer, separated from thefirst to the seventh gate members, insulated from the first to thefourth semiconductor members, overlapping the third and the fourthsemiconductor members, respectively; and sixth and seventh connectionsformed on the second layer and connecting the fifth and the sixth gatemembers to the eighth and the ninth gate members, respectively.

The TFT array panel may further include: tenth and eleventh gate membersformed on the first layer, insulated from the first to the fourthsemiconductor members and overlapping the third and the fourthsemiconductor members, respectively; twelfth and thirteenth gate membersformed on the first layer, separated from the first to the eleventh gatemembers, and insulated from the third and the fourth semiconductormembers, the twelfth and the thirteenth gate members not overlapping thefirst to the fourth semiconductor members; and eighth and ninthconnections formed on the second layer and connecting the tenth and theeleventh gate members to the twelfth and the thirteenth gate members,respectively.

The TFT array panel may further include a seventh connection formed onthe second layer and connecting the third semiconductor member and thefourth semiconductor member.

The first data member may be connected to the first and the thirdsemiconductor members, and the TFT array panel may further include asecond data member connected to the second and the fourth semiconductormembers and insulated from the first to the thirteenth gate members. Thefirst data member preferably transmits a gate-off voltage for tuning offa thin film transistor and the second data member preferably transmits agate-on voltage for turning on the thin film transistor.

The TFT array panel may further include: a first insulating layerinterposed between the first and the second semiconductor members andthe first and the second gate members; and a second insulating layerinterposed between the first and the second gate members and the firstdata member, wherein the second insulating layer has a first contacthole for connecting the first gate member and the second gate member,and the first and the second insulating layer has a second contact holefor connecting the first data member and the one of the first and thesecond semiconductor members.

A method of manufacturing a thin film transistor (TFT) array panel isprovided, which includes: forming a blocking layer on a substrate;,depositing an amorphous silicon film on the blocking layer;crystallizing the amorphous silicon film into a polysilicon film;patterning the polysilicon film to form first and second polysiliconmembers; forming a gate insulating layer on the first and the secondpolysilicon members; forming a plurality of first conductive membersoverlapping the first and the second polysilicon members; forming aplurality of second conductive members not overlapping the first and thesecond polysilicon members; implanting N type impurity to form aplurality of N type impurity regions in the first polysilicon member;implanting P type impurity to form a plurality of P type impurityregions in the second polysilicon member; depositing an interlayerinsulating layer on the first and the second conductive members and theN type and the P type impurity regions; patterning the interlayerinsulating layer and the gate insulating layer to form a plurality offirst contact holes exposing portions of the first and the secondconductive members and to form a plurality of second contact holesexposing portions of the N type and the P type impurity regions; forminga plurality of connections connected to the first and the secondconductive members through the first contact holes; and forming aplurality of data members connected to the N type and the P typeimpurity regions through the second contact holes.

The N type impurity implantation precedes or follows the P type impurityimplantation.

The data members may include first and second voltage lines respectivelyconnected to the N type and the P type impurity regions for transmittingfirst and second voltages; and may include a connecting member connectedto both the N type impurity region and the P type impurity region.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describingembodiments thereof in detail with reference to the accompanyingdrawings in which:

FIG. 1 is a schematic diagram of a TFT array panel according to anembodiment of the present invention;

FIG. 2A is an exemplary layout view of a driving circuit area of apolysilicon TFT array panel;

FIG. 2B is a sectional view of the driving circuit area shown in FIG. 2Ataken along the line IIB-IIB′;

FIGS. 3A, 4A and 5A are layout views of a TFT array panel inintermediate steps of a manufacturing method thereof; and

FIGS. 3B, 4B and 5B are sectional views of the TFT array panel shown inFIGS. 3A, 4A and 5A taken along the lines IIIB-IIIB′, IVB-IVB′ andVB-VB′, respectively.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the inventions are shown.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present.

Now, polysilicon TFT array panels and manufacturing methods thereofaccording to an embodiment of the present invention will be described indetail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a TFT array panel according to anembodiment of the present invention.

Referring to FIG. 1, a TFT array panel according to an embodiment of thepresent invention includes a display area A provided with a plurality ofpixel electrodes (not shown), a plurality of TFTs (not shown) forswitching electrical signals supplied to the pixel electrodes, and aplurality of signal lines such as a plurality of gate lines (not shown)and a plurality of data lines (not shown) for transmitting the signalsto the TFTs, and a plurality of driving circuit areas B provided with aplurality of circuit elements for controlling the signals supplied tothe display area A. The circuit elements on the driving circuit areas Binclude a plurality of TFTs.

An exemplary configuration of the driving circuit areas B according toan embodiment of the present invention is described in detail withreference to FIGS. 2A and 2B.

FIG. 2A is an exemplary layout view of a driving circuit area of apolysilicon TFT array panel, and FIG. 2B is a sectional view of thedriving circuit area shown in FIG. 2A taken along the line IIB-IIB′.

As shown in FIGS. 3A and 3B, a blocking layer 111 is formed on atransparent insulating substrate 110. A pair of first and secondsemiconductor members 151 a and 151 b and a pair of third and fourthsemiconductor members 152 a and 152 b are formed on the blocking layer111. The first and second semiconductor members 151 a and 151 b haveopposite conductivity, while the third and fourth semiconductor members152 a and 152 b also have opposite conductivity.

A gate insulating layer 140 is formed on the semiconductor members 151a, 151 b, 152 a and 152 b (abbreviated as 151 a-152 b) preferably madeof polysilicon, and a plurality of gate members 121 a, 121 b, 122 a, 122b, 123 a, 123 b and 123 f (abbreviated as 121 a-123 f) are formed on thegate insulating layer 140.

The gate members 121 a-123 f include a first group of gate members 121 aand 121 b, a second group of second gate members 122 a and 122 b, and athird group of third gate members 123 a, 123 b and 123 f located betweenthe first group of the gate members 121 a and 121 b and the second groupof the gate members 122 a and 122 b in the first direction.

The first group of gate members 121 a and 121 b includes first controlelectrodes 121 a intersecting the first and the second semiconductormembers 151 a and 151 b and first control lines 121 b, which do notoverlap the semiconductor members 151 a-152 b.

The second group of gate members 122 a and 122 b includes second controlelectrodes 122 a overlapping the third and the fourth semiconductormembers 152 a and 152 b, and second control lines 121 b, which do notoverlap the semiconductor members 151 a-152 b.

The third group of gate members 123 a, 123 b and 123 f includes thirdcontrol electrodes 123 a intersecting the first and the thirdsemiconductor members 151 a and 152 a, fourth control electrodes 123 foverlapping the second and the fourth semiconductor members 151 b and152 b, and a third gate line 123 b, which does not overlap thesemiconductor members 151 a-152 b.

The first and the third control electrodes 121 a and 123 a partitioneach of the first and the second semiconductor members 151 a and 151 binto three portions, i.e., upper, middle and lower portions, which aredoped with N type impurity. Like wise, the third and the second controlelectrodes 123 a and 122 a partition the third semiconductor member 152a into upper, middle and lower portions, which are doped with N typeimpurity, and the fourth and the second control electrodes 123 f and 122a partition the fourth semiconductor member 152 b into upper, middle andlower portions. However, portions of the semiconductor members 151 a-152b under the control electrodes 121 a, 122 a, 123 a and 123 f are notdoped.

An interlayer insulating layer 160 is formed on the gate members 121a-123 f. The interlayer insulating layer 160 has a plurality of contactholes 161 a-161 d exposing the gate members 121 a-123 f, and the gateinsulating layer 140 and the interlayer insulating layer 160 have aplurality of contact holes 162 a-162 h exposing the semiconductormembers 151 a-152 b. In detail, the contact holes 161 a, 161 c and 161 dexpose the control electrodes 121 a, 122 a, 123 a and 123 f, while thecontact holes 161 b expose the control lines 121 b, 122 b and 123 b. Thecontact holes 162 a and 162 b expose the upper portions of the first andthe second semiconductor members 151 a and 151 b, respectively, and thecontact holes 162 c and 162 d expose the lower portions of the first andthe second semiconductor members 151 a and 151 b, respectively. Thecontact holes 162 e and 162 f expose the upper portions of the third andthe fourth semiconductor members 152 a and 152 b, respectively, and thecontact holes 162 g and 162 h expose the lower portions of the third andthe fourth semiconductor members 152 a and 152 b, respectively.

A plurality of data members 121 c, 122 c, 123 c-123 e and 170 a-170 d(abbreviated to 121 c-170 d) are formed on the interlayer insulatinglayer 160.

The data members 121 c-170 d include first gate connections 121 c, 122 cand 123 c connected to the respective control electrodes 121 a, 122 aand 123 a through the contact holes 161 a and connected to therespective control lines 121 b, 122 b and 123 b through the contactholes 161 b, and it also includes second gate connections 123 d and 123e connected to the third control electrodes 123 a through the contactholes 161 c and 161 d, respectively, and connected to the fourth controlelectrodes 123 f through the contact holes 161 a.

The data members 121 c-170 d further includes a first voltage line 170 atransmitting a gate-off voltage (or Vss voltage) for turning off theTFTs on the display area A and connected to the upper portions of thefirst and the second semiconductor members 151 a and 151 b through therespective contact holes 162 a and 162 b, and a second voltage line 170d transmitting a gate-on voltage (or Vdd voltage) for turning on theTFTs on the display area A and connected to the lower portions of thethird and the fourth semiconductor members 152 a and 152 b through therespective contact holes 162 g and 162 h.

In addition, the data members 121 c-170 d include first and secondoutput electrodes 170 b and 170 c connected to the lower portions of thefirst and the second semiconductor members 151 a and 151 b through therespective contact holes 162 c and 162 d and connected to the upperportions of the third and the fourth semiconductor members 152 a and 152b through the respective contact holes 162 e and 162 f.

Each of the first semiconductor members 151 a-152 b and the controlelectrodes 121 a and 123 a or 122 a and 123 a form double TFTs connectedin parallel. The TFTs including the first and the second semiconductormembers 151 a and 151 b are N type transistors, while the TFTs includingthe third and the fourth semiconductor members 152 a and 152 b are Ptype transistors. Therefore, the output electrodes 170 b and 170 calternatively outputs the gate-off voltage (or Vss voltage) and thegate-on voltage (or Vdd voltage) in response to the operations of theTFTs.

As described above, the control electrodes 121 a, 122 a, 123 a and 123 fand the control lines 121 b, 122 b and 123 b are connected via theseveral connections 121 c, 122 c and 123 c-123 e. Accordingly, thedamages on the semiconductor members due to electrostatic chargesintroduced through the control lines 121 b, 122 b and 123 b can bereduced.

Although it is not shown in the figures, the gate lines and the datalines on the display area A are preferably made of the same layers ofthe gate members 121 a-123 f, the data members 121 c-170 d. Furthermore,the TFTs on the display area A preferably have the same layeredstructure as the TFTs on the driving circuit areas B.

An additional insulating layer may be formed on the data members 121c-123 f if it is required particularly in the display area A.

A method of manufacturing a TFT array panel including the circuit areashown in FIGS. 2A and 2B according to an embodiment of the presentinvention is described in detail with reference to FIGS. 3A-5B as wellas FIGS. 2A and 2B.

FIGS. 3A, 4A and 5A are layout views of a TFT array panel inintermediate steps of a manufacturing method thereof, and FIGS. 3B, 4Band 5B are sectional views of the TFT array panel shown in FIGS. 3A, 4Aand 5A taken along the lines IIIB-IIIB′, IVB-IVB′ and VB-VB′,respectively.

Referring to FIGS. 3A and 3B, a blocking layer 111 and an amorphoussilicon film is deposited on a transparent insulating substrate 110. Theamorphous silicon film is crystallized into a polysilicon film by heattreatment using laser annealing or furnace. The polysilicon film ispatterned to form first and second polysilicon members 150 a and 150 b.A plurality of polysilicon members (not shown) for TFTs on a displayarea A are also formed in this step.

Referring to FIGS. 4A and 4B, a gate insulating layer 140 preferablymade of SiO₂ or SiN_(x) is formed on the polysilicon members 150 a and150 b. A metal layer is deposited on the gate insulating layer 140 andpatterned to form a plurality of gate members 121 a-123 f including aplurality of control electrodes 121 a, 122 a, 123 a and 123 f and aplurality of control lines 121 b, 122 b and 123 b.

Next, N type impurity implantation is performed using the gate members121 a-123 f as an implantation mask to form first and secondsemiconductor members 151 a and 151 b from the polysilicon member 150 a.At this time, the polysilicon members 150 b may be blocked by aphotoresist pattern. Thereafter, a photoresist pattern (not shown) isformed on the first and the second semiconductor members 151 a and 151 band P type impurity implantation is performed to third and fourthsemiconductor members 152 a and 152 b. The sequence of N type impurityimplantation and P type impurity implantation may be changed.

At this time, since the gate members 121 a-123 f are divided intoseveral pieces, electrostatic charges are not transferred to thesemiconductor members 151 a-152 b. In particular, the electrostaticcharges introduced in the control lines 121 b, 122 b and 123 b, whichare relatively long and large, are hardly transferred to the controlelectrodes 121 a, 122 a, 123 a and 123 f since they are separated fromthe control lines 121 b, 122 b and 123 b. Although the charges aretransferred to the control electrodes 121 a, 122 a, 123 a and 123 f, thesemiconductor members 151 a-152 b may not be damaged since the controlelectrodes 121 a, 122 a, 123 a and 123 f are too small and short and thedifference in the area between the control electrodes 121 a, 122 a, 123a and 123 f is too small to generate voltage difference sufficient fordamaging the semiconductor members 151 a-152 b.

Referring to FIGS. 5A and 5B, an interlayer insulating film 160 isformed on the semiconductor members 151 a, 151 b, 152 a and 152 b andphoto-etched along with the gate insulating layer 140 to form aplurality of contact holes 161 a-161 d and 162 a-162 h exposing the gatemembers 121 a-123 f and the semiconductor members 151 a, 151 b, 152 aand 152 b.

Finally, a metal layer is formed on the interlayer insulating layer 160and patterned to form a plurality of data members 121 c-170 d as shownin FIGS. 2A and 2B.

As described above, since the gate members are divided into severalpieces, electrostatic charges are not transferred to the semiconductormembers. In addition, although the charges are transferred to thecontrol electrodes, the semiconductor members may not be damaged sincethe control electrodes are too small and short to generate voltagedifference sufficient for damaging the semiconductor members.

While the present invention has been described in detail with referenceto the embodiments, those skilled in the art will appreciate thatvarious modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A thin film transistor (TFT) array panel, comprising: an insulatingsubstrate; first and second semiconductor members formed on thesubstrate and having opposite conductivity; a first gate member formedon a first layer, insulated from the first and the second semiconductormembers and overlapping one of the first and the second semiconductormembers; a second gate member formed on the first layer, separated fromthe first gate member, and insulated from the first and the secondsemiconductor members, the second gate member not overlapping the firstand the second semiconductor members; a first data member formed on asecond layer, connected to one of the first and the second semiconductormembers and insulated from the first and the second gate members; and afirst connection formed on the second layer and connecting the firstgate member and the second gate member.
 2. The TFT array panel of claim1, wherein the first and the second semiconductor members comprisepolysilicon.
 3. The TFT array panel of claim 2, wherein the first gatemember overlaps the first semiconductor member.
 4. The TFT array panelof claim 3, further comprising a third gate member formed on the firstlayer, separated from the first and the second gate members, insulatedfrom the first and the second semiconductor members, and overlapping thesecond semiconductor member.
 5. The TFT array panel of claim 4, furthercomprising a second connection formed on the second layer and connectingthe second gate member and the third gate member.
 6. The TFT array panelof claim 4, further comprising: a fourth gate member formed on the firstlayer, separated from the first, the second, and the third gate membersand insulated from the first and the second semiconductor members, thefourth gate member not overlapping the first and the secondsemiconductor members; and a second connection formed on the secondlayer and connecting the third gate member and the fourth gate member.7. The TFT array panel of claim 6, further comprising: fifth and sixthgate members formed on the first layer, separated from the first to thefourth gate members, insulated from the first and the secondsemiconductor members, and overlapping the first and the secondsemiconductor members, respectively; a seventh gate member formed on thefirst layer, separated from the first to the sixth gate members andinsulated from the first and the second semiconductor members, theseventh gate member not overlapping the first and the secondsemiconductor members; and third and fourth connections formed on thesecond layer and connecting the fifth and the sixth gate members to theseventh gate member.
 8. The TFT array panel of claim 7, furthercomprising a fifth connection formed on the second layer and connectingthe first semiconductor member and the second semiconductor member. 9.The TFT array panel of claim 8, further comprising: third and fourthsemiconductor members formed on the substrate and having oppositeconductivity; eighth and ninth gate members formed on the first layer,separated from the first to the seventh gate members, insulated from thefirst to the fourth semiconductor members, overlapping the third and thefourth semiconductor members, respectively; and sixth and seventhconnections formed on the second layer and connecting the fifth and thesixth gate members to the eighth and the ninth gate members,respectively.
 10. The TFT array panel of claim 9, further comprising;tenth and eleventh gate members formed on the first layer, insulatedfrom the first to the fourth semiconductor members and overlapping thethird and the fourth semiconductor members, respectively; twelfth andthirteenth gate members formed on the first layer, separated from thefirst to the eleventh gate members, and insulated from the third and thefourth semiconductor members, the twelfth and the thirteenth gatemembers not overlapping the first to the fourth semiconductor members;and eighth and ninth connections formed on the second layer andconnecting the tenth and the eleventh gate members to the twelfth andthe thirteenth gate members, respectively.
 11. The TFT array panel ofclaim 10, further comprising a tenth connection formed on the secondlayer and connecting the third semiconductor member and the fourthsemiconductor member.
 12. The TFT array panel of claim 11, wherein thefirst data member is connected to the first and the third semiconductormembers.
 13. The TFT array panel of claim 12, further comprising asecond data member connected to the second and the fourth semiconductormembers and insulated from the first to the thirteenth gate members. 14.The TFT array panel of claim 13, wherein the first data member transmitsa gate-off voltage for turning off a thin film transistor and the seconddata member transmits a gate-on voltage for turning on the thin filmtransistor.
 15. The TFT array panel of claim 1, further comprising: afirst insulating layer interposed between the first and the secondsemiconductor members and the first and the second gate members; and asecond insulating layer interposed between the first and the second gatemembers and the first data member, wherein the second insulating layerhas a first contact hole for connecting the first gate member and thesecond gate member, and the first and the second insulating layer has asecond contact hole for connecting the first data member and the one ofthe first and the second semiconductor members.